The present invention relates to a memory system, and more particularly to an address control circuit for designating a memory block to be subjected to data exchange with a main memory.
Computer system includes a main memory which is connected to a central processing unit (CPU) via a bus. While operation speed of the CPU has become very fast, the operation speeds of the bus and the main memory are still low. Therefore, it is difficult to transfer data between the CPU and the main memory at the high operation speed of the CPU. A high speed memory called a cache memory has been proposed to be inserted between the CPU and the main memory, so that the CPU may directly have interface with the cache memory at a high speed. The capacity of the cache memory is limited and small. Therefore, the cache memory stores a relatively small quantity of data which are read from the main memory. In order to implement the above function of the cache memory, the storage addresses of the cache memory are divided into a plurality of areas. Namely, memory cells of the cache memory are divided into a plurality of memory cell blocks. A control circuit is provided to the cache memory for designating the memory cell block or area to be accessed by the CPU according to the history of the access or utilization of the respective memory cell blocks or the areas. Namely, the order of the utilization of the respective cell blocks are stored in a control memory and the cell block which stores the oldest information, or, which is not utilized by the CPU most recently, is subjected to rewriting contents thereof in accordance with the contents of the main memory. The control memory includes a plurality of memory cells for storing the accessed order of the respective cell blocks, and the least recently utilized cell block (storing the oldest information) is designated by the control memory.
However, the conventional control memory fails to designate the cell block storing the oldest information in a certain case and the effective data exchange of information is not achieved between the cache memory and the main memory. For example, when a power supply to the control memory is switched on, the states of the respective memory cells in the control memory are made uncertain and the control memory cannot designate the cell block storing the oldest information.